ISEPS / Curriculum / Module 04
Module 04 of 06
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Introduction to VLSI Design

10 h Online 5 h Onsite 15 h Total
Overview

What you will study

Introduction to VLSI design presents how modern integrated circuits are conceived, designed, verified, and prepared for fabrication, with emphasis on the practical constraints that limit microelectronics designs. The course discusses contemporary IC application domains and explains the industrial ecosystem around chip creation, including IP blocks, the fabless model, PDKs, and the path from specification to tape out and manufacturing.

Building on device level fundamentals, the lecture introduces the most important chip active and passive components and highlights key non-idealities such as short-channel and layout-dependent effects, parasitics, and noise that determines real circuit behavior. Students learn how technology variability is handled through process corners and statistical models, and how design trade-offs motivate modern design methodologies.

The course connects device physics to circuit level building blocks used in VLSI systems, covering representative analog and digital structures and their timing, stability, and robustness considerations. It also introduces the fundamentals of IC testing and design for testability (DFT), including fault concepts and scan based approaches. Overall, the goal is to give students a clear view of integrated circuit design process, from devices and circuit designs to manufacturability and tests.

Topics Covered

Key topics

Faculty

Module lecturers

Piotr Mierzwiński
Piotr Mierzwiński
Assistant Professor
Warsaw University of Technology
He graduated from the Faculty of Electronics and Information Technology at Warsaw University of Technology. In 2023, he received his PhD for a dissertation entitled Bipolar Transistor in VESTIC Technology. Since January 2023, he has been affiliated with the Institute of Microelectronics and Optoelectronics at Warsaw University of Technology, where he currently works as an Assistant Professor. His research interests include device physics and modelling, numerical simulations, compact models, and the analysis of prototype structures and measurements. He is also involved in analog and mixed-signal integrated circuit design. He is particularly interested in open-source EDA tools and conducts classes related to integrated circuit design and contemporary electronic design methodologies.
KS
Krzysztof Siwiec
Assistant Professor
Warsaw University of Technology
He received the M.Sc. degree and the Ph.D. (with honors) in electronic engineering from the Warsaw University of Technology, Poland, in 2010 and 2016 respectively. His doctoral research was related to frequency synthesis for low power wireless communication. Since 2016 he has been assistant professor at the Institute of Microelectronics and Optoelectronics (VLSI Engineering and Design Automation Division). He is working on analog and mixed-signal circuits for biomedical signal measurement and acquisition, targeting wearables and IoT applications. In 2016 he cofounded ChipCraft, a Polish fabless semiconductor company, where he holds the position of CTO.
Igor Butryn
Igor Butryn
Assistant Professor
Warsaw University of Technology
He is a graduate of the Faculty of Electronics and Information Technologies at Warsaw University of Technology (WUT). In 2023, he was awarded the PhD degree for a dissertation on the design of integrated LC oscillators for wireless transceivers. Since 2024, he has been employed as an Assistant Professor at the Institute of Microelectronics and Optoelectronics. His research focuses on the design of analog and mixed-signal integrated circuits, particularly frequency synthesis circuits, wireless transceivers and cryptographic components.
Schedule

Module 04 Schedule

Hour breakdown for this module across online and onsite delivery formats.

Topic / Session
Online
Onsite
Total
Introduction to VLSI Design
10 h
5 h
15 h
Module Total
10 h
5 h
15 h

Ready to apply for ISEPS?

20 places available · Hybrid format · Warsaw University of Technology

Co-funded by the European Union · European Funds for Social Development · Republic of Poland